The PCI Base Address Register (BAR)
in Myrinet PCI64 interfaces

This documentation applies to all of Myricom's PCI64 family of 64-bit Myrinet/PCI interfaces (PCI64, PCI64A, and PCI64B).

These interfaces provide a 64-bit PCI Base Address Register (BAR) in order to allow for future hosts and operating systems that may require a 64-bit BAR. However, all of the interfaces in the PCI64 family will also function properly when programmed with a 32-bit address, per the PCI specifications.

A mechanical switch on the circuit board allows selecting between a 64-bit BAR or a 32-bit BAR. The 32-bit BAR function is necessary to accommodate operating systems and firmware that either cannot properly load a 64-bit address into a 64-bit BAR, or cannot correctly write a 32-bit address into a 64-bit BAR. Here are examples of the BAR switch:

BAR switch on an M3M-PCI64B interface. Similar labeling is used on other PCI64B interfaces. This switch is set to a 32-bit BAR.

BAR switch on an M2L-PCI64A interface. The switch is labeled as "J4," and the "DBL" indicates a 64-bit BAR setting. This switch is set to a 32-bit BAR.

Interfaces are shipped with the BAR switch in the 32-bit position, the preferred mode for all current platforms and operating systems. Some OS/platforms can accept a 64-bit BAR, but the 64-bit BAR provides no additional capability.

Platform	Operating System	Preferred BAR setting
Alpha	Linux	32-bit
	Tru64	32-bit
x86	Linux	32-bit
	NT 4	32-bit
	Solaris	32-bit
	Windows 2000	32-bit
PowerPC	Linux	32-bit
	VxWorks	32-bit
UltraSPARC	Solaris (32-bit)	32-bit
SPARC64	Linux (Ultrapenguin)	32-bit
	Solaris 7 (64-bit)	32-bit
SGI O200	Irix 6.4/6.5	32-bit

Last Updated: 27 July 2000